SPI Clock Divider Calculator

How STM32 SPI prescalers work

STM32 SPI peripherals derive SCLK from the APB peripheral clock via the BR[2:0] field in SPI_CR1. The three bits select a power-of-two prescaler:

Formula: SCLK = PCLK / 2^(BR+1)

In C, set it before enabling the peripheral:

/* Select ÷4 (BR=1) on SPI1 */
SPI1->CR1 &= ~SPI_CR1_BR_Msk;
SPI1->CR1 |= (1U << SPI_CR1_BR_Pos);  /* BR[2:0] = 001 */
SPI1->CR1 |= SPI_CR1_SPE;             /* enable */

With STM32 HAL, set hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4 before calling HAL_SPI_Init(). The HAL macro values are SPI_BAUDRATEPRESCALER_2 through SPI_BAUDRATEPRESCALER_256.

Note that the STM32 reference manual specifies a maximum SCLK — typically fPCLK/2 — so BR=000 is the maximum. You cannot run SPI faster than half the peripheral clock.

Which PCLK feeds your SPI peripheral?

This is the most common source of confusion on STM32:

STM32F4: SPI1, SPI4, SPI5, SPI6 run on APB2 (up to 84 MHz at 168 MHz system clock). SPI2 and SPI3 run on APB1 (up to 42 MHz). Check RCC_APB1ENR and RCC_APB2ENR to see which enable bits map to which peripherals.

STM32G0/G4: All SPI peripherals share a single APB clock domain (up to 64 MHz on G0, 170 MHz on G4). Consult your specific device’s clock tree in the datasheet.

STM32H7: The SPI peripherals can be clocked from different sources via the RCC_D2CCIP1R register — not just the APB clock. CubeMX handles this for you, but be aware the actual source may differ from the bus clock.

Use STM32CubeMX’s clock tree view to verify the actual peripheral clock frequency before running the calculator.

nRF52 SPIM: fixed frequencies, not a divider

The nRF52 SPIM peripheral does not have a programmable prescaler. Instead, the FREQUENCY register takes a fixed 32-bit constant from a small enumerated set:

NRF_SPIM0->FREQUENCY = 0x80000000UL;  /* 8 Mbps */
NRF_SPIM0->FREQUENCY = 0x40000000UL;  /* 4 Mbps */
NRF_SPIM0->FREQUENCY = 0x20000000UL;  /* 2 Mbps */
NRF_SPIM0->FREQUENCY = 0x10000000UL;  /* 1 Mbps */
/* etc. */

The constants are defined in nrf52840.h as SPIM_FREQUENCY_FREQUENCY_M8 through SPIM_FREQUENCY_FREQUENCY_K125. Any other value written to the register produces an undefined clock — do not treat these as continuous register values.

In Zephyr, set the frequency via the device tree: clock-frequency = <4000000>; in your SPI node, or pass it in the spi_config struct at runtime.

The maximum SPIM frequency on nRF52840 is 8 Mbps. The nRF5340 SPIM4 peripheral supports 32 Mbps, but that’s a different register map entirely.

Why you always pick SCLK ≤ fSCLK_max

SPI slaves specify a maximum clock frequency in their datasheet electrical characteristics, usually under conditions of VCC min, worst-case temperature, and maximum capacitive load. Exceeding this limit leads to setup/hold violations at the slave’s data input — you’ll see intermittent bit errors, often appearing only after the board warms up or at low supply voltage.

The “floor” mode in this calculator finds the fastest achievable SCLK that does not exceed your target. This is the safe default. Use “nearest” mode only if you’re characterising a device and want to know the closest achievable frequency in either direction.

Common scenario: a W25Q128 NOR flash is rated 104 MHz at VCC = 2.7–3.6 V. With STM32F4 APB2 at 84 MHz, the maximum achievable SPI clock is 42 MHz (÷2). That’s well within spec. On a ÷1 configuration — which the STM32 doesn’t even support — you’d need to verify the 84 MHz timing against the flash’s 104 MHz spec at your voltage.

Common mistakes

Wrong PCLK on STM32. Using the wrong APB clock is the most frequent error. A beginner configures PCLK2 = 84 MHz but routes their SPI2 through APB1 = 42 MHz, then wonders why CubeMX calculates a different baud rate than their manual calculation. Always verify via HAL_RCC_GetPCLK1Freq() / HAL_RCC_GetPCLK2Freq() at runtime if in doubt.

Ignoring capacitive load. At high SCLK frequencies, PCB trace length and connector capacitance matter. Above 10 MHz on anything but short traces, add series termination resistors (22–33 Ω) on SCLK, MOSI, and CS lines. A 10 MHz signal through 10 cm of FR4 trace and a 10 pF load at the slave pin can produce a rise time longer than the setup time requirement, especially with 3.3 V CMOS logic.

Forgetting CPOL/CPHA setup time. Changing SCLK frequency doesn’t change the CPOL/CPHA mode — but at higher speeds the setup time from CS assert to first clock edge (tCSS, typically 50–100 ns on flash devices) becomes harder to meet. Some devices require a delay between CS assert and the first clock edge. Software-controlled CS via GPIO is slower than hardware NSS, so at 20+ MHz, hardware NSS may be necessary.

nRF52: using the SPI (not SPIM) peripheral. The legacy SPI peripheral tops out at 8 Mbps and is deprecated. Use SPIM0–SPIM3. On nRF52840, SPIM3 supports high-speed mode up to 32 Mbps with a dedicated clock.

Common SPI device speed limits