What does the −3 dB cutoff frequency mean in practice?

At fc, the output amplitude is 1/√2 (≈70.7%) of the input, which corresponds to −3.01 dB. In terms of power, it's exactly half. For a debounce filter at 159 Hz, button bounces above 159 Hz are attenuated but not eliminated — a first-order RC only rolls off at −20 dB/decade. Bounces at 10× fc (1.6 kHz) are attenuated by 20 dB to about 10% amplitude. Software debouncing still handles the rest.

Why does my ADC read noise even with an RC anti-alias filter?

The RC filter only attenuates frequencies above fc — it doesn't eliminate them. A first-order filter gives −20 dB/decade, so signals at 10× fc come through at 10% amplitude, at 100× fc at 1% amplitude. For a 12-bit ADC with 1 kHz fc, a 10 kHz interference signal is attenuated by 20 dB (10% amplitude), which is still 1.25 LSBs on a 12-bit ADC with a 3.3 V reference and 1 mV noise. If you need more attenuation, use a second-order RC (two stages) or an active Sallen-Key filter.

How do I pick the right R and C values for a debounce filter?

Set fc between 10–100 Hz for mechanical buttons. Bounce duration is typically 1–10 ms, so a τ = 1 ms (fc ≈ 159 Hz) with R = 10 kΩ, C = 100 nF is a common starting point. The GPIO input capacitance (2–5 pF typical) is negligible at these impedance levels. Avoid very low R values ( 100 kΩ) — they make the filter sensitive to leakage currents and PCB contamination.

What is the rise time of an RC filter and how does it relate to fc?

Rise time (10% to 90%) = 2.197 × τ = 2.197 × RC = 0.35 / fc. This is the same relationship used in oscilloscope bandwidth calculations. An oscilloscope with 100 MHz bandwidth has an RC-equivalent rise time of 3.5 ns. For a debounce filter with τ = 1 ms, the rise time is 2.2 ms — meaning a clean button press takes about 2.2 ms to register.

RC Filter / Time Constant Calculator

Frequency	f / fc	Attenuation	Gain
15.92 Hz	0.1×	-0.0 dB	99.5%
79.58 Hz	0.5×	-1.0 dB	89.4%
159.2 Hz ← fc	1×	-3.0 dB	70.7%
318.3 Hz	2×	-7.0 dB	44.7%
795.8 Hz	5×	-14.1 dB	19.6%
1.592 kHz	10×	-20.0 dB	10.0%

Application	R	C	fc	τ
Button debounce	10.0 kΩ	100 nF	159.2 Hz	1 ms
ADC anti-alias (1 kSps)	1.00 kΩ	100 nF	1.592 kHz	100 µs
ADC anti-alias (audio)	4.70 kΩ	10 nF	3.386 kHz	47 µs
GPIO noise filter	1.00 kΩ	10 nF	15.92 kHz	10 µs
Power supply bypass	100 Ω	10 µF	159.2 Hz	1 ms
MCU RESET de-glitch	10.0 kΩ	100 nF	159.2 Hz	1 ms
RF decoupling	10.0 Ω	100 pF	159.2 MHz	1 ns

How it works

An RC filter is a resistor and capacitor in series. The output is taken either across the capacitor (low-pass) or across the resistor (high-pass).

The time constant:

τ = R × C

The −3 dB cutoff frequency:

fc = 1 / (2π × R × C) = 1 / (2π × τ)

At f = fc, the output amplitude is 0.707× (−3 dB) and the phase shift is −45°. Below fc the signal passes through; above fc it’s attenuated at −20 dB per decade.

Low-pass vs high-pass

Low-pass (capacitor to GND): blocks high frequencies, passes DC and low frequencies. The capacitor is a short circuit at high frequencies, pulling the output to GND. Use for debounce, ADC anti-aliasing, power supply noise filtering.

High-pass (capacitor in series): blocks DC and low frequencies, passes high frequencies. The capacitor blocks DC. Use for AC coupling, removing DC offset from sensor signals, high-frequency signal extraction.

Step response timing

When a step voltage is applied:

t_rise (10→90%)  = 2.197 × τ
t_settle (to 1%) = 4.605 × τ
t_settle (to 0.1%) = 6.908 × τ

These come from V(t) = V_in × (1 − e^(-t/τ)). Solving for 10%, 90%, 99%, and 99.9% output gives the multipliers above.

Frequency response

A first-order RC rolls off at −20 dB per decade. At 10× fc, attenuation is −20 dB (10% amplitude). At 100× fc it’s −40 dB (1% amplitude). For steeper roll-off, cascade two RC stages (second-order, −40 dB/decade) or use an active filter (Sallen-Key, MFB).

Common use cases in embedded systems

Button debounce. Mechanical buttons bounce for 1–10 ms. An RC low-pass at 100–500 Hz (τ = 0.3–1.6 ms) charges the capacitor slowly enough to smooth out the bounce pulses. R = 10 kΩ, C = 100 nF gives fc = 159 Hz and τ = 1 ms. The GPIO still needs a Schmitt trigger input to give a clean digital edge — most STM32 and nRF52 GPIO inputs have this.

ADC anti-alias filter. The Nyquist theorem requires all frequencies above half the sample rate to be attenuated before the ADC. For a 1 kSps ADC, set fc < 500 Hz. STM32 ADC with 12-bit resolution at 3.3 V has 1 LSB = 0.8 mV — anything above Nyquist that folds back in will add noise. R = 1 kΩ, C = 100 nF gives fc = 1.59 kHz — appropriate for audio-range sampling (8 kSps, Nyquist = 4 kHz). Keep R low enough that the driving impedance stays within the ADC’s R_AIN_max spec (typically 10–50 kΩ for STM32, check the ADC chapter in the reference manual).

Power supply bypass. After an LDO or buck converter, an RC low-pass on the supply rail to a sensitive analog section reduces switching noise. R = 10–100 Ω, C = 10 µF gives fc = 160–1600 Hz. The resistor must be sized to handle the load current: at 100 mA through 10 Ω, the voltage drop is 1 V — only viable if the supply has headroom.

I2C / SPI bus filtering. On long PCB traces or in noisy environments, a 100 Ω series resistor and 100 pF to GND on SCL/SDA reduces ringing. This gives fc ≈ 16 MHz — well above the 400 kHz I2C bus speed, so it won’t distort the signal but will dampen high-frequency ringing.

MCU RESET de-glitch. The RESET pin on most MCUs expects a clean low pulse. Short power glitches cause spurious resets. R = 10 kΩ, C = 100 nF gives a τ = 1 ms filter — any glitch shorter than 1 ms won’t pull RESET low long enough to trigger a reset. Check the datasheet for the minimum RESET pulse width (nRF52840: 100 µs minimum; STM32 varies by family).

Common mistakes

Using a voltage divider to set the filter midpoint. An RC filter works from a voltage source. If you put a voltage divider before the RC, the output impedance of the divider becomes part of R in the filter. R_eff = R_top ∥ R_bot. Account for this or the fc will be lower than expected.

Ignoring the ADC’s input capacitor. STM32 ADC inputs have a sample-and-hold capacitor (2–8 pF internal, plus pin capacitance). This capacitor charges through the filter R and the external series resistor. If R is too high, the hold capacitor doesn’t fully charge during the sample time, causing conversion errors. The ADC chapter in the reference manual specifies R_AIN_max — keep your series resistor below this.

Expecting sharp roll-off from a single-pole filter. One RC stage gives −20 dB/decade. For interference 10× above fc, attenuation is only 20 dB. On a noisy bench or in an automotive environment, that’s often not enough. Two cascaded RC stages (second-order) give −40 dB/decade but the first stage’s output impedance loads the second — recalculate, or use a buffer in between.

Forgetting temperature and tolerance. Ceramic capacitors (X5R, X7R) change capacitance with temperature and DC bias. A 100 nF X5R at 3.3 V bias and 85°C might be 70 nF in practice, shifting fc by 30%. For precision filter cutoffs, use film capacitors (polypropylene, polyester) or NP0/C0G ceramics.

RC Filter / Time Constant Calculator

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Result

Frequency Response

Common RC Filter Applications