Your I2C sensor initialises fine on the bench, fails in the field. Or you add a second device to the bus and everything becomes unreliable. Or SDA stays low after a power cycle. In almost every case, pull-up resistors are involved.
How pull-ups actually work
I2C uses open-drain signalling. Neither the master nor any slave ever drives the bus high — they only pull it low. The pull-up resistors pull SDA and SCL back to VCC when nobody is driving. If the resistors are wrong, the bus can’t reach a valid logic-high level fast enough (or at all).
The rise time is governed by the RC time constant: τ = R × C. The I2C spec defines maximum rise times — 1000 ns for standard mode (100 kHz), 300 ns for fast mode (400 kHz), 120 ns for fast-mode plus (1 MHz). Exceed these and the receiver missamples bits.
Too high: the slow-rise problem
A 10 kΩ pull-up on a bus with 100 pF of capacitance gives τ = 1 µs. That’s marginal at 100 kHz and broken at 400 kHz. Symptoms:
- Works with one device, fails with two (more capacitance)
- Works at 100 kHz, fails at 400 kHz
- Works when wires are short, fails when you add a cable
- Intermittent ACK failures after transactions start correctly
On a scope, look at the rising edge of SCL or SDA. It should be a sharp ramp, not a gentle curve that barely reaches VCC before the next clock edge.
Too low: the current problem
A 100 Ω pull-up on a 3.3 V bus means the bus sources 33 mA when a device pulls it low. Most I2C devices specify maximum sink current of 3–10 mA. Below 470 Ω the voltage at the device pin won’t reach a valid low (V_OL is specified against a load, and I²C devices can’t sink unlimited current).
Symptoms of too-low pull-ups: devices get warm, bus appears to work initially then stops, or VOL measurements show the “low” level sitting at 0.5–1.0 V instead of near ground.
The capacitance budget
Bus capacitance comes from:
- PCB trace capacitance (~1 pF/cm for standard FR4 traces)
- Device pin capacitance (5–15 pF per device, per datasheet)
- Connector and cable capacitance (if applicable)
The I2C spec allows 400 pF maximum bus capacitance. At that load, standard 4.7 kΩ pull-ups at 100 kHz are borderline. Use the I2C pull-up resistor calculator to find the valid range for your specific capacitance and speed.
The voltage translation trap
If you have a 5 V device and a 3.3 V MCU on the same bus, do not use a resistor divider or a diode in series. Use a proper level translator with open-drain-compatible bidirectional channels (BSS138-based designs work well). A direct connection pulls the MCU’s 3.3 V SDA line to 5 V, which is out-of-spec on most devices and will damage some.
Debugging a locked-up bus
SDA stuck low after a power cycle or failed transaction means a slave is mid-transaction and holding SDA down waiting for more clocks. The fix:
// Toggle SCL 9 times to flush any stuck slave state
// Then generate a STOP condition
// Most I2C peripherals have a bus recovery sequence in their driver
// On STM32 HAL:
HAL_I2C_DeInit(&hi2c1);
// Manually bit-bang 9 clocks on the SCL pin
for (int i = 0; i < 9; i++) {
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_SET);
HAL_Delay(1);
HAL_GPIO_WritePin(SCL_GPIO_Port, SCL_Pin, GPIO_PIN_RESET);
HAL_Delay(1);
}
// Generate STOP: SDA low → SCL high → SDA high
HAL_I2C_Init(&hi2c1);On nRF52, the TWIM peripheral has a TASKS_RESUME and error recovery built into the SDK via nrfx_twim_disable / nrfx_twim_enable.
Quick diagnostics
- Measure rise time on a scope — should be < 300 ns at 400 kHz
- Measure VOH with a multimeter — should be within 0.1 V of VCC under light load
- Check VOL — should be < 0.4 V at the specified sink current
- Count devices and trace length — feed into the calculator to verify your resistor value is in range
- Test isolation — disconnect devices one at a time to find which one is loading the bus
The I2C spec is more tolerant than people think on timing, but the DC levels and capacitance budget are hard limits. Get those right and most flakiness disappears.